Shashanka K M
ASIC Design Engineer - l (DFT) | DFT implementation, BSCAN, timing constraints analysis, ijtag, JTAG, SCAN, ATPG. IEEE 1149.6
- Role
- Asic Design Engineer - L (Dft) at Alphawave Semi
- Location
- Mysuru, KA, IN
- LinkedIn followers
- 500 followers
About Shashanka K M
Alphawave Semi leverages contributions in block-level DFT implementation, including scan insertion, ATPG, and timing constraints analysis. Collaborated on top-level BSCAN and debugging efforts, aligning deliverables with 1149.6, and 1687 standards. Academic foundation in Electronics and Communication Engineering underpins a strong understanding of DFT methodologies. Hands-on experience with industry tools like Tessent, Spyglass, and Xcelium supports high-quality design workflows. Dedicated to advancing semiconductor testing standards through innovation and precision.
Experience
Asic Design Engineer - L (Dft)
May 2024 — Present · Bengaluru, IN
I worked on the block level DFT implementation (scan,atpg,DRC) and chip top level BSCAN and timing constraints analysis
Education
Visvesvaraya Technological University
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
2017 — 2021
NMAM Institute of Technology
Bachelor of Engineering - BE, Electronics and communication engineering
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