Shashank Shrivastava

About Shashank Shrivastava

14+ Years of Experience in Functional Verification at Block,IP, Sub-Systerm, Full-Chip and Full-System Level. Hands on Experience with Low Power Verification at both RTL and netlist level and Formal Verification as well. Worked on Full Verification Cycles covering from developing VIPs to Functional Coverage and closure with VHDL +OSVVM and SV + VMM/OVM/UVM. Experience with Protocols like PCI,PCIe,I2C, AHB, AXI,AXI Stream and SATA. Worked on Inter-Processor Communication with Interrupt Handlers. Working Knowledge on MIPI CSI-2, D-PHY, CXL, eMMC and USB as well. Worked on Cryptographic algorithms, X-prop simulations and Performance Verification as well. Elementary knowledge on JTAG and 5G.

Experience

1. Senior Technical Lead

   Wipro

   Jun 2023 — Present · Bengaluru, IN

   Performance Verification, AI

Education

• BIT Durg

  Bachelor of Engineering (B.E.), Electronics and Telecommunication Engineering

  2002 — 2006

• IIIT Hyderabad

  Master of Technology (M.Tech.), VLSI and Embedded Systems

  2007 — 2009

Skills

• Tcl
• Soc
• Physical Design
• Vlsi
• Very-Large-Scale Integration (Vlsi)
• Debugging
• Application-Specific Integrated Circuits (Asic)
• Processor Design
• Rtl Coding
• Design Compiler
• Xilinx
• Systemverilog
• Sata
• Hardware Architecture
• Formal Verification
• C
• Low-Power Design
• Arm
• Modelsim
• Functional Verification
• Amba Ahb
• Fpga
• Asic
• Open Verification Methodology
• Rtl Design
• Processors
• Pcie
• I2c
• Verilog
• Ncsim
• Vmm
• Pci Express
• System Verilog
• Semiconductors
• Field-Programmable Gate Arrays (Fpga)
• Compilers
• Logic Synthesis
• Timing Closure
• Logic Design
• Integrated Circuit Design