Shashank Kumaravelu

WORK HISTORY

EDUCATION

SKILLS

ABOUT SHASHANK KUMARAVELU

Hi, Welcome to my profile!I am a Graduate student with major in Electrical Engineering at University of Southern California (Expected graduation date: May 2017) focussing on VLSI System Design and Computer Architecture. Enriched my skills and got an opportunity to apply my theoretical knowledge as SoC design Intern at Simple Inc. Also, have 3 years of work experience in PLC programming, logic design and troubleshooting practices with OMPL.Actively looking for Full time position in the following domains.• ASIC Design and Verification.• RTL Design • Physical and Logic Design.• Computer Architecture.Extensive knowledge in Pipeline Process architecture, FIFO design, Cache Memory, timing checks and hands on experience in logic synthesis with Xilinx ISE, Design simulation with Model Sim, Verilog, C/C++, Perl scripting for design automation.Technical Proficiency:HDL: Verilog, VHDLEDA Tools: Cadence NCSim, Synopsys DC,Cadence Encounter & Synopsys Primetime.Programming Languages: Perl, Python, Verilog, C++, PLC Programming, DCS, C, Java (Blue J), IDE/Tools/Framework: Deter Lab, Cadence Virtuoso, ModelSim, Xilinx ISE, Spectre, MATLAB, Honeywell system Manager, Experion PKS, HMI builder, Honeywell DCS, Siemens SimaticS7, Schneider Modicon, Triconex, Woodward Governor Speed Control,Corporation Antisurge Control and GE Cimplicity. Personal skills: • Quick learner, eager to further my technical knowledge and skills.• Meticulous worker; attentive to detail.• Able and willing to assist co-workers, supervisors, and clients in a cooperative manner.• Committed to providing total quality work.I can be reached at (21••••••90 or by email at k•••••••@usc.edu.