Shashank Joisa

About Shashank Joisa

Silicon Engineer with 3+ years of experience working on Design verification of GPU IP and DFT MBIST, performed regression analysis at SoC as part of internship. I have done functional verification of Complex Memory Subsystem Hubs.Working on Nvidia proprietary and AMBA CHI protocols. Veryifying IP to the depth of each clock is my job.I am team player and have leadership skill.In quest of challenging opportunities related to ASIC Designing in leading electronics industries.I have completed my Master\'s in VLSI Designs and Embedded Systems at BITS Pilani, Hyderabad Campus. I have academic knowledge with coursework and projects on VLSI Design, VLSI Architecture, Reconfigurable Computing, and Embedded Systems.I am the best at what I do.

Experience

1. Asic Engineer

   NVIDIA

   Aug 2023 — Present · Bengaluru, IN

   Debugged and analyzed 200+ regression failures, detecting RTL bugs using simulation logs and Verdi. Created simple VIP for scoreboard purpose• Experienced with one complete cycle of DGPU chip process, CHI (AMBA) protocol, valid-credit, valid-ready protocol. Implemented assertion based, randoms, deadlock based verification methodologies• Created testbench in UVM for new features in DGPU memory subsystem IP and verified performance signals of the DGPU, IGPU IP using perl framework.• Added coverage testcases and analyzed various scenarios in register verification, BLCG and improved coverage from 60% to 95%.• Experienced with writing tcl scripts for SFV and SLCG SFV, for multiple modules using Jasper Gold and detected/resolved various RTL bugs.• Worked on bringing up and debugging gate level synthesis and x-propagation, hence verifying RTL. Ran formality check post FNL.• Used perl-verilog based wrapper to write SFV assertions and coverpoints to reduce verification effort by 50%• Worked on Cursor AI with integration of perforce, DVT and many other productivity extensions.

Education

• RNS Institute of Technology - India

  Bachelor of Engineering - BE, Electronics and Communication Engineering

  2014 — 2018

• BITS Pilani, Hyderabad Campus

  Master of Engineering - MEng, Embedded Systems