Sharvari Surendra

About Sharvari Surendra

With over 6 years of hands-on experience in the technology industry, I have consistently…

Experience

1. Physical Design Engineer

   Intel

   Sep 2020 — Present · IN

   During my time at Intel, I played a pivotal role in the development and deployment of cutting-edge technologies across multiple advanced nodes, ensuring the highest quality standards and driving cross-functional collaboration. I spearheaded the Intel 18A, 7nm, 4nm, and 3nm projects, focusing on clock tree synthesis, timing analysis, and custom routing for DDR PHY IP.In the Intel 18A project, I constructed a robust clock tree spine for the main clocks in DDR PHY IP, performing static timing analysis, PT simulations, and RV analysis to meet stringent timing and power requirements. I designed and implemented a clock tree spine structure, ensuring balanced skew and optimized insertion delay, which contributed significantly to meeting timing closure targets. My collaboration with RTL, Analog, and verification teams was instrumental in integrating clocking strategies and resolving performance bottlenecks.For the Intel 7nm and 4nm projects, I led the synthesis, floorplanning, placement, clock tree synthesis, routing, and timing closure of a partition in DDR PHY IP. I integrated mixed signal components, constructed a high-frequency clock tree spine, and addressed timing DRCs and layout violations to deliver a PV clean design. My efforts included developing Tcl scripts for custom routing and ensuring minimal impact on layout despite RTL updates.In the Intel 3nm project, I implemented complex functional ECOs, reduced derates, and managed PDK updates, addressing all timing and caliber violations. My signal integrity analysis and strategic placement of critical nets ensured robust performance. I contributed to the tape out of three chips, meeting aggressive PPA and schedule goals through the effective use of Fusion Compiler and Primetime tools.