Sharvani Mukkala
- Role
- Mts Silicon Design Verification Engineer at AMD
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Sharvani Mukkala
Design Verification Engineer with 10 years of work experience. Skillset- UVM,OVM…
Experience
Mts Silicon Design Verification Engineer
Nov 2021 — Present
Low power digital IP verification engineer -Responsible for testplan developement, documentation and execution -Responsible for coverage closure, gatesim and cosim verification of IPs -Setting up of the regression suite,release gate and other infrastructure needed for the IP
Skills
- Systemverilog
- Verilog
- Vhdl
- System Verilog
- Microsoft Office
- Asic
- Windows
- Vlsi
- Perl Script
- Matlab
- Microsoft Excel
- C++
- C
- Linux
- Verilog Hdl
- Electrical Engineering
- Mips
- Ovm
- Cadence
- Perl
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