Sharath Koodali Edathil
- Role
- Principal Layout Designer at Arm
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Principal Layout Designer
Jan 2016 — Present
Skills
- Calibre
- Vlsi
- Circuit Design
- Debugging
- C
- Processors
- Cadence Virtuoso
- Dfm, Em, Place & Route
- Eda
- Static Timing Analysis
- Very-Large-Scale Integration (Vlsi)
- Cadence
- Design Rule Checking (Drc)
- Standard Cell Layout Architecture, Standard Cell Layout Development
- Layout
- Tool & Flow Debugging
- Standard Cell
- Physical Verification
- Uderstanding of Calibre Design Rule Coding (Svrf)
- System on a Chip (Soc)
- Development Tools
- Verilog
- Cadence Skill
- Shell
- Automation Using Perl, Shell and Cadence Skill Scripting Languages
- Application-Specific Integrated Circuits (Asic)
- Page Layout
- Asic
- Drc
- Semiconductors
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