Sharath Bp
SoC Design Engineer : Physical Design
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sharath Bp
Experienced in Low power design and Memory Circuit design. Worked on power estimation/rollup/optimization for SoC\'s. Power optimization at synthesis and PnR stages. Power estimation for various test cases was done using Synopsys PT-PXKnowledge on complete ASIC physical design implementation flow.Worked on the development of ROM memory, involved in the leaf cell designs such as control block, pre-decoder block, local control block and sense amplifier design. Understanding of complete signal flow in the memory architecture.Worked on sense amplifier offset analysis, bitcell analysis and circuit checks analysis.
Experience
Soc Design Engineer
May 2018 — Present · Bangalore, IN
Education
Vellore Institute of Technology
Master of Technology (MTech), VLSI DESIGN
2014 — 2016
APS college of engineering
Bachelor of Engineering (B.E.), Telecommunications Engineering
2009 — 2013
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