Shanuj Garg
Member of Technical Staff (MTS) Analog Design Engineer at AMD | ex-Qualcomm | ex-arm
- Role
- Mts Silicon Design Engineer at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Shanuj Garg
Technical experience in memory circuit design, Analog Design, verification and characterization with a demonstrated history of working in the semiconductors industry. Skilled in Cadence Virtuoso ADE (analog design environment), Mentor Eldo Spice and Monte Carlo by Solido. Strong engineering professional with a Master of Engineering (M.Eng.) focused in Microelectronics Engineering from Birla Institute of Technology and Science, Pilani.
Experience
Mts Silicon Design Engineer
Sep 2024 — Present · Bengaluru, IN
Analog Design Engineer specializing in Security IPs against frequency attacks and SerDes high-speed TX design, with focus on robust analog/mixed-signal implementations.
Education
Birla Institute of Technology and Science, Pilani
Master of Engineering (M.Eng.), Microelectronics Engineering
2014 — 2016
National Institute of Technology Surat
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
2009 — 2013
Kendriya Vidyalaya
Higher Secondary, physics chemistry and mathematics stream
2007 — 2009
Skills
- Cadence Virtuoso
- Modelsim
- Ni Multisim
- Mathematical Logic
- Multisim
- Eldo
- Logics
- Analog Circuit Design
- Microsoft Excel
- Circuit Design
- Keil
- Verilog
- Pspice
- Vlsi Cad
- 8051 Microcontroller
- C
- Programming
- Vlsi
- Digital Electronics
- Cadence Virtuoso Layout Editor
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