Shannon Kesner
PMTS Server DDR Validation and Debug Lead at AMD
- Role
- Pmts Server Ddr Validation and Debug Lead at AMD
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Shannon Kesner
Skills: pre-silicon planning, post-silicon execution/validaton, circuit board design
Experience
Pmts Server Ddr Validation and Debug Lead
Jan 2015 — Present
Education
The University of Texas at Austin
Master's, Electrical Engineering
2010 — 2013
University of Florida
Bachelor's, Electrical Engineering
1996 — 2001
Skills
- Semiconductors
- Hardware Design
- System Testing
- Computer Architecture
- Schematic Capture
- Debugging
- Microprocessors
- Hardware Support
- Verilog
- Technical Documentation
- Hardware Architecture
- Processors
- Fpga
- Soc
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