Naveen Pathak
CPU Architecture Verification, Test Plans, Stimulus Development | FPGA Developer | CNN Architectures
- Role
- Junior Research Fellow at Iit Jammu
- Location
- New Delhi, DL, IN
- LinkedIn followers
- 500 followers
About Naveen Pathak
Naveen Pathak 96••••••76 Professional Summary A highly skilled and…
Experience
Junior Research Fellow
Jan 2025 — Present
Custom RISC-V Architecture Development: Leading the full-stack design and implementation of a flexible, high-performance RISC-V core, built from scratch.Native CNN Acceleration: Integrated convolution operations directly into the RISC-V pipeline, enabling high-speed execution of CNN workloads.Peripheral Interface Design: Developed custom I/O and control peripherals for a tailored SoC built on RISC-V, boosting system-level integration.VGG16 Hardware Architecture: Engineered a dedicated hardware implementation of VGG16; currently advancing through validation and pre-tapeout optimization stages.Toolchain & Compiler Co-Design: Collaborating on a custom compiler stack using Bluespec, Verilator, and ModelSim, enabling seamless hardware-software co-verification.
Education
Bundelkhand University
Bachelor of Technology, Electronics and Communications Engineering
2014 — 2018
Indian Institute of Technology, Delhi
Doctor of Philosophy - PhD, Mx Signal Design
Sunbeam English School
intermediate, PCM
2012 — 2014
National Institute of Technology Delhi
Master of Technology - MTech, VLSI
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