Shankar S
Senior Verification Engineer - Asic verification
- Role
- Senior Design Verification Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Shankar S
Experienced Senior Verification Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Application-Specific Integrated Circuits (ASIC), Perl, and System on a Chip (SoC).
Experience
Senior Design Verification Engineer
Dec 2023 — Present · Bengaluru, IN
Education
Anna University Bachelor of engineering SKR engg college
Bachelor of Engineering (BEng), Electronics and Communications Engineering
2009 — 2013
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.