Shambhavi Kulkarni

About Shambhavi Kulkarni

SoC design engineer with 13 years of experience in physical design. Taped out multiple complex chips on leading process nodes. Strong knowledge of tools, methodologies and flows resulting in quick turnaround time of designs.

Experience

1. Physical Design Integration Enginner

   Intel

   Jan 2011 — Present

   STRENGTHS- Full Chip Design Planning leveraging SoC architectural knowledge and data flows- Bump planning for chiplets to enable optimum 2.5D SoC package- Experience on 18A/intel3/intel4/10nm/14nm/32nm and TSMC 5nm/7nm process- Synthesis and Automated place and route (APR), Performance verification- Expertise in Physical design flows driving solutions for global SoC implementation challenges- Mentoring junior engineers on design methodology and concepts.• Full Chip Design Planning- Owned Full Chip Design Planning fusion compiler database and responsible for TD collateral delivery to partition owners for APR implementation- Collaborated with IP teams to finalize placement on SoC according to Hard IP Integration guideline requirements including bump planning, special cells and critical signal routing- Designed Logical and physical Channels based on data flow across various design blocks, pin congestion, data connectivity and repeater delay stages- Created multiple die files and worked with Package team for package routing analysis for PCIE/ETHERNET/UCIE/DDR PHY placements, orientations, power bump planning and EMIB routing.• Full chip Tasks - FC FEV: Enabled and owned Full chip FEV flow and found real issues in signal connectivity for channel partitions- Worked on different aspects of Full chip Layout verification related to collateral cleanliness and systematic issues in APR flow causing DRC, DEN and NAC violations- Created Etch ring, EDM, PRS components to meet manufacturing requirements and analyzed base layer DRC violations for assembly.• Partition Owner- Owned complete execution of multiple partitions from floor planning to final timing and LV closure- Physical design implementation using IC compiler/IC compiler II starting from netlist to GDS including floorplanning, placement strategies, clock optimization and analysis, solving complex placement and routing issues in multiple partitions.

Education

• University of Cincinnati

  Master of Science - MS

  2008 — 2010

• Shivaji University

  Bachelor Of Engineering

  2003 — 2007

Skills

• Asic
• Static Timing Analysis
• Perl
• Tcl
• Modelsim
• Application-Specific Integrated Circuits (Asic)
• System on a Chip (Soc)
• Verilog
• Vlsi
• C
• Spice