Shalini Singh

About Shalini Singh

projects - 1) Decimation Clock Domain Crossing Design TOP LEVELDetails : Dealing with different clock domain frequency, need to send data from 192 MHz frequency to 12 MHz frequency then to 3 MHz frequency deviceclient location: SONY JAPAN (offsite)skills: Digital microarchitecture, verilog, system verilog, functional coverage, assertion, sta2)Digital FIR Filter DesignDetails: converting 12MHz frequency into 3MHz frequency by using FIRclient location : SONY JAPAN (offsite)skills:verilog, system verilog, assertion, coverage, static timing analysis3)Digital CIC FILTERS DESIGNDetails: Filter converting 192 MHz to 12MHzclient location: SONY JAPAN (offsite)skills: verilog, system verilog, assertion, coverage, Static timing analysis4)IMAGE SENSING CAMERA DESIGN 8 MEGA PIXELSDetails :12 Bit DEFECTS PIXELS CORRECTIONclient: Integrated Device Technology JAPANskills: verilog, system verilog, assertion, coverage, Static timing analysis5)AHB2APB Bridge IP Core VerificationDetails:HVL: System Verilog TB Methodology: UVM EDA Tool: Riviera Pro - Aldec Description: The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses- Architected the class based verification environment in UVM- Defined Verification Plan - Verified the RTL module with UVM Test Bench with different test scenarios like single READ, WRITE & Burst READ, WRITE with different burst lengths- Generated functional and code coverage for the RTL verification sign-off. Responsibilities- Architected the class based verification environment in UVM- Defined Verification Plan - Verified the RTL module with UVM Test Bench with different test scenarios like single READ, WRITE & Burst READ, WRITE with different burst lengths- Generated functional and code coverage for the RTL verification sign-off. 6) Router 1x3 - RTL design and VerificationDetails:Router 1x3 - RTL design and Verification HDL: Verilog HVL: SystemVerilog TB Methodology: UVM EDA Tools: Questasim and ISE Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.

Experience

1. Graphics Hardware Engineer

   Intel

   Apr 2020 — Present · Bangalore, IN

Education

• RGTU

  Master of Technology - MTech

  2016 — 2018

• Rajiv Gandhi Prodyogiki Vishwavidyalaya

  Bachelor of Engineering - BE