Shalini Nanda

About Shalini Nanda

Senior Technical Team Lead with 8+ years of mixed signal layout experience in analog and IO. Major contribution in power modules (LDO, BGR), High frequency layouts upto 24GHz (SERDES, PLL, RF amplifier, oscillators), DACs, IO ESD layouts (GPIO, LVDS), etc and Layout Automation for increasing productivity. Experience in leading multiple customer projects (managing upto 12+ team) for major product companies.In depth knowledge of layout design at deep sub-micron technologies, fdsoi, and finfet nodes from 350nm to 6nm.

Experience

1. Senior Technical Team Lead

   HCLTech

   Apr 2021 — Present · Bangalore Urban, IN

Education

• Silicon Institute of Technology (SIT), Bhubaneswar

  Bachelor of Technology - BTech

  2009 — 2013

Skills

• Lvs
• C++
• Serdes
• Debugging
• Mixed Signal
• Floorplanning
• Bicmos
• Application-Specific Integrated Circuits (Asic)
• Matlab
• Physical Verification
• Dac
• Analog Circuit Design
• Semiconductors
• Design Rule Checking (Drc)
• Drc
• Fpga
• Cmos
• Phase-Locked Loop (Pll)
• Pll
• C
• Very-Large-Scale Integration (Vlsi)
• Vhdl
• Layout Versus Schematic (Lvs)
• Physical Design
• Static Timing Analysis
• Linux
• Modelsim
• Perl
• Embedded Systems
• Cadence Virtuoso
• Verilog
• System on a Chip (Soc)
• Electronics