Shakti Chaganty

About Shakti Chaganty

Physical Design Engineer with hands on experience on Clock design and implementation, block convergence, floor planning and automation.Hands on experience on custom clock design for large complex floorplans and inter die clocking.Experienced in Block ownership through tape-in on 7nm and 10nm.Adept at Power, Performance, Area trade-offs and design feasibility analysis.Proficient in RTL to GDSII physical design flows.Owned complex partitions through closure on 10nm and 7nm process nodes.Understanding of overall IC Design flow and EDA tools used in Physical Design Implementation. Knowledge of effects of technology scaling on Power, Performance and Reliability of CMOS circuits.TOOLS:Synopsys Design Compiler, ICC2, PrimeTime, PTPX, Conformal LEC, Calibre, Cadence ADE-XL, VirtuosoLanguages:Verilog, TCLContact info:Email : s••••••••@gmail.com

Experience

1. Physical Design Engineer

   Apple

   Jan 2023 — Present · Austin, TX, US

Education

• University of Utah

  Master's Degree, Computer Engineering

  2013 — 2015

• Jawaharlal Nehru Technological University

  Bachelor's Degree, Electrical and Electronics Engineering

  2009 — 2013

Skills

• Vlsi
• Cadence Virtuoso
• Verilog
• Static Timing Analysis
• Physical Design
• Embedded Systems
• Altium Designer
• Cmos
• Analog Circuit Design
• Synplify Pro
• Cad of Digital Circuits
• C
• Pspice
• Fpga
• Orcad Capture Cis
• Python
• Matlab
• Automation
• Pcb Population
• Pcb Layout Design
• Teamwork
• Public Speaking
• Soldering
• C++
• Algorithms
• Linux
• Programming
• Simulations
• Testing
• Emacs