Shakti Somadutt Rout

About Shakti Somadutt Rout

I am a results-driven engineering leader with 13+ years of experience in semiconductor and wearable technologies, currently driving verification excellence at Qualcomm. My journey has spanned from SoC-level leadership to IP-level technical depth, giving me a unique ability to balance strategic oversight with hands-on expertise.At Qualcomm, I progressed from Senior Lead Engineer to Staff Engineer, expanding my perspective across complex SoC programs and specialized IP verification. I have: • Led global teams of 30+ engineers on XR platforms, Security SoCs, and Smart Wearable projects. • Transitioned to leading Security IP verification (ICE, QRNG) with a 5-member team, where I drive cost-saving initiatives and deliver industry-leading quality standards. • Directed verification of critical IPs like Crypto, RNG, Secure Processor, and Trust Management, ensuring robustness in next-generation devices.My experience combines: • Breadth → leading full SoC verification, low-power strategies, and cross-functional collaboration. • Depth → specializing in security IPs, verification methodologies, and cost optimization. • Impact → reducing expenses, improving efficiency, and delivering high-quality silicon solutions.I am passionate about building and leading high-performing teams and advancing verification methodologies that shape the future of connected and secure devices. With my proven track record of scaling leadership and deepening expertise, I am ready to take the next step as a Senior Staff Engineer.

Experience

1. Staff Engineer

   Qualcomm

   Dec 2024 — Present · Bengaluru, IN

   As a Staff Engineer, I lead a specialized team focused on security IP verification, ensuring reliability and robustness of critical IPs such as ICE and QRNG. I drive both technical execution and strategic initiatives, aligning verification practices with industry-leading standards to enhance product quality and reduce costs.Key Highlights: • Led verification of security IPs (ICE, QRNG), ensuring compliance with performance, security, and quality benchmarks. • Directed a 6 member team, providing technical guidance, mentorship, and process alignment to maximize efficiency. • Championed cost-optimization initiatives that significantly reduced company expenses while maintaining top-tier verification standards. • Implemented quality improvement measures that strengthened product reliability and reduced risk of field issues. • Collaborated with cross-functional teams to streamline verification flows, driving consistent delivery of high-quality IPs.

Education

• B D B P Tangi

  HSC, Matriculation

  2002

• Prana Nath Autonomous College, Khurda

  Intermediate, science

  2002 — 2004

• Biju Patnaik University of Technology, Odisha

  Bachelor of Technology (BTech), Electronics and Telecommunication

  2006 — 2010

• Veer Surendra Sai University Of Technology ( Formerly UCE ), Burla

  Master of Technology (MTech), Communication System Engineering

  2011 — 2013

Skills

• Matlab
• Vcs
• Sva
• Modelsim
• Apb
• Perl
• Axi 4
• Vhdl
• Code Coverage
• Debugging
• Functional Verification
• Ovm
• Functional Coverage
• Research
• Cadence
• Mvsim
• Vmm
• Systemverilog
• Altera Quartus
• Teaching
• Universal Verification Methodology (Uvm)
• Verilog
• Vlsi
• Soc
• Ovm
• Fpga
• Asic
• Cmos
• Arm Architecture
• Mvsim
• Mvrc
• Rtl Design
• Questasim
• Uvm
• Xilinx Ise
• System Verilog
• System on a Chip (Soc)