Shaishav Shah

About Shaishav Shah

Experienced and leading Digital Systems- Microarchitecture and RTL Design with a demonstrated history of working in the semiconductors industry. Owned multiple IP Logic Design for Qualcomm Snapdragon Mobile processors, Modem, IOT, Special Chips.Strong engineering professional with a Master of Technology (MTech) focused in Microelectronics and VLSI from IIT Bombay.Owned Micro Architecture and RTL preparation from Specifications, Design Documentation.NoCs, Bridges, Pipes and Fabric IP design for Modem, IOTs, and Mobile Processor SoC, Debug and Silicon.Coding experience in Verilog.Experienced in CDC, Linting, Synthesis.Past aditional experience in Intel for-Processor Core IP Integration, Datapath design.Scripting using Perl & Python.PDN & Reliability Validation for Processor Core IP.STA and Formal Equivalence Verification.Skills experienced in:Interconnect Protocols- AMBA- AXI, AHB, APB, Packetization.NoC topology, architecture design and Performance monitor.Micro-Architecture Development.RTL CodingLinting.CDC.Sythesis.Scripting.Simulation & Debugging.PDN and RV.STATools Experienced in:Spyglass, Verdi & 0in.ISE, ModelSim.Shell, Perl & Python Scripting. RedhawkClearcase & Clearquest.Git

Experience

1. Asic Rtl Design Engineer

   Google

   Sep 2021 — Present · Bengaluru, IN

   Working in ASIC Front End IP Design/RTL Design Domain.

Education

• Indian Institute of Technology, Bombay

  Master of Technology (MTech), Microelectronics and VLSI

  2013 — 2015

• The Maharaja Sayajirao University of Baroda

  Bachelor of Engineering (BEng), Electronics Engineering

  2009 — 2013

Skills

• C
• Html
• Linux
• Systemc
• Python
• Matlab
• Very-Large-Scale Integration (Vlsi)
• Vhdl
• C++
• Tcl
• Analog
• Verilog
• Perl
• Embedded Systems
• Assembly Language