Shailesh Pathak

About Shailesh Pathak

SOC Design and Integration o Full Chip RTL Integration o Interconnect Design for SOC(AMBA Designer) o NOC based Interconnect Design(ARTERIS FlexNoC) o Functional ECO in various netlist view of SOC design cycle o Full Chip CDC (Methodology development and Analysis) o Full Chip LINT (Strategy and analysis) o Chip Level STA and DFT support o Chip Level Dynamic CDC analysis support o Netlist verification with post layout SDFs o Technology porting of Vendor IPs o Floor Plan Analysis and PPA o Integration qualification Video/Audio display interface digital IP design Set-top box sub-systems eMMC/SD controller digital IP Update Knowledge of Video/Audio standards o HDMI, Display Port Standard, ITU-R, SMPTE and CEA standards Knowledge of Bus Interfaces o APB, AXI Interfaces, NIC-400 Interconnect o Interconnect generation with AMBA Design(NIC-400) o NOC base Interconnect generation using ARTERIS IP procurement Front End ASIC design implementation of IPs/Sub-systems o RTL Code(VHDL, Verilog ),Synthesis (RTLcompiler/DC), STA, Linting (Spyglass) o Expertise in Micro-architecture with multiple clock and power domains o Expertise in Complete IP Cores development flow from System requirements to Silicon Validation. o Synthesis (DC, RC), Conformal ECO o Formal Verification(Formality & Conformal) o Timing Analysis (Primetime) o DFTProject/People Management : Specifications of IP o Drive the discussion with system and IP architect to develop the specification o Involve with driver and validation team to final closure of specification o Defining the micro-architecture and writing micro-architecture specification of IPs Project planning and tracking Synchronizing the design, FE and BE activities of the projects* Have filed two patents (Both granted by USPTO)

Experience

1. Engineer, Principal Manager

   Qualcomm

   Dec 2022 — Present

Education

• Madan Mohan Malviya Engineering College, Gorakhpur

  B.E., Electronics & Communication

  1996 — 2000

Skills

• Formal Verification
• Static Timing Analysis
• Timing Closure
• Hardware Architecture
• Eda
• Logic Synthesis
• Vhdl
• Ic
• Arm Architecture
• Dft
• Functional Verification
• Primetime
• Systemverilog
• Tcl
• Asic
• Rtl Design
• Integrated Circuit Design
• Low-Power Design
• System on a Chip (Soc)
• Arm
• Verilog
• Application-Specific Integrated Circuits (Asic)
• Vlsi
• Very-Large-Scale Integration (Vlsi)
• Digital Signal Processors
• Rtl Coding
• Ncsim
• Cmos
• Integrated Circuits (Ic)
• Soc