Shahryar Aryani
- Role
- Dft at Synopsys Inc
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Shahryar Aryani
My experience has been in design-for-test (DFT), both as a design engineer and as an…
Experience
Dft
Sep 2014 — Present
As part of the AMD PHY IP team who joined Synopsys!
Skills
- Ic
- Soc
- Social Skills
- Physical Design
- Asic
- Functional Verification
- Semiconductors
- Vlsi
- Cmos
- Verilog
- Dft
- Fpga
- Rtl Design
- Sram
- Systemverilog
- Static Timing Analysis
- Debugging
- Eda
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