Shah Jahinuzzaman
Principal Engineer @Intel
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WORK HISTORY
Principal Engineer @Intel
Hillsboro, OR, US
EDUCATION
University of Waterloo
Master's Degree, Electrical and Computer Engineering
University of Waterloo
PhD, Electrical and Computer Engineering
Bangladesh University of Engineering and Technology
BSc, Electrical & Electronic Engineering
SKILLS
ABOUT SHAH JAHINUZZAMAN
Technical leader advancing the performance frontier and reliability of server SoCs through technology and circuit innovations. Strong background in transistor technology, digital circuit design, and reliability mechanisms across FinFET and Gate-All-Around (GAA) process nodes.Proven track record in Design-Technology Co-Optimization (DTCO), including 2.5D/3.5D integration, on-die power delivery network (PDN) optimization, IR drop/EM mitigation, and soft error rate (SER) reduction. Combines hands-on technical depth with strategic leadership, driving technology-pathfinding initiatives that bridge research innovation with manufacturable, reliable, and scalable silicon solutions.Experienced in industry-standard simulation tools, silicon bring-up, and post-silicon test & debug. Recognized for role modeling data-driven decision-making, disciplined execution, and effective cross-geo collaboration.4 granted U.S. patents | 20+ scholarly publications
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