Shafaat Ahmed

About Shafaat Ahmed

I am a Principal Engineer with over 15+ years of experience across Intel, GlobalFoundries, and IBM, specializing in advanced semiconductor packaging, chiplet integration, and interconnect reliability. I am currently focused on enabling packaging architectures for large-scale AI and high-performance compute systems.My work has centered on enabling scalable high-performance systems through technologies such as EMIB, Foveros, and advanced BEOL integration. I have led development efforts that bridge process, design, and system architecture—solving critical challenges in bandwidth scaling, power delivery, thermal management, and manufacturability.I bring deep expertise in multi-die system integration, including tradeoffs between modular (bridge-based) and monolithic (interposer-based) architectures. My contributions have supported both internal product development and foundry customers, driving technologies from pathfinding through PRQ and into high-volume manufacturing.I hold 50+ patents and disclosures and have published extensively in the field, with over 1600 citations. I am particularly interested in applying advanced packaging and system integration to next-generation AI hardware, where performance is increasingly defined by interconnect, memory bandwidth, and packaging innovation.I enjoy working at the intersection of materials, process, and system architecture to deliver practical, scalable solutions for complex technologies.

Experience

1. Principal Engineer (Emib-t, Foveris, Maxmim Yield and Integration Td)

   Intel

   Mar 2024 — Present · NM, US

   Lead advanced packaging integration for EMIB and Foveros platforms, enabling scalable chiplet-based architectures for high-performance compute systems• Drive system-level tradeoffs across interconnect density, power delivery, thermal constraints, and reliability for large multi-die integration• Enable scaling beyond reticle limits using modular packaging strategies (EMIB vs interposer approaches)• Solve critical yield and reliability challenges (electromigration, stress, defectivity), accelerating technology readiness ahead of PRQ timelines• Collaborate with design, PDK, and product teams to implement chip–package co-design methodologies• Support Intel Foundry Services customers with advanced packaging and BEOL integration strategies

Education

• Bangladesh University of Engineering and Technology

  BSc in Materials and Metallurgical Engineering, Materials/Metallurgy

  1995 — 2000

• University of Limerick

  PhD, Applied Physics ( Materials Physics & Electrochemistry)

  2001 — 2004

Skills

• Project Management
• Technical Leadership
• Thin Films
• Characterization
• Spectroscopy
• Materials Science
• Failure Analysis
• Energy
• Semiconductors
• Electroplating
• Spc
• Powder X-Ray Diffraction
• Process Engineering
• Afm
• Research and Development (R&D)
• R&D
• Research
• Cmos
• Photovoltaics
• Product Development
• Physics
• Strategy
• Business Strategy
• Nanomaterials
• Nanotechnology
• Management
• Data Analysis
• Six Sigma
• Chemistry
• Process Integration
• Statistical Process Control (Spc)
• Sem
• Process Improvement
• Cross-Functional Team Leadership
• Program Management
• Solar Cells
• Electrochemistry
• Materials
• Science
• Ic