Shabari Girish

About Shabari Girish

Passionate towards VLSI Front end Design and Verification, where I can efficiently contribute my skills at my work as well as continue to develop my abilities to match with the latest trend in the industry.2. Having 9+ years of experience in VLSI Design & Verification. Architecting & Developing Verification environment using SV & UVM. Development of Verification plan.5. Hands on experience with EDA tool - Verdi,VCS[Dve],Xilinx and Questasim. Good Understanding of HVL concepts. Experience in coding test scenario using verification plan. Experience in functional coverage, RAL, assertions and constraint driven randomization. Good programming skills in complex HVL test bench modules like monitors, BFMs etc, from the given verification plan and functional coverage modules based on coverage plan. Experience in industry standard protocols like CMI, APB, SCI and UART. Experience in DDR Memory subsystem, Power management and Automotive IPs. Experience synopsis certitude, TE_Linter for test bench quality check. Experience GLS and Xprop simulations. Good Understanding of FSM based RTL design. Good knowledge of SOC, Subsystem,IP, ASIC and FPGA verification flow.

Experience

1. Senior Pre-silicon Verif-val Engineer

   Intel

   Dec 2020 — Present · Bengaluru, IN

   Intel Pre-Silicon Verification | ASIC/SOC/IP/Subsystems

Education

• Sri Ramakrishna Vidyanikethan

  SSLC

  2000 — 2008

• Visvesvaraya Technological University

  BE, Electronics and Communications Engineering

  2010 — 2014

• Maven silicon softech pvt ltd

  Advanced VLSI design and verification course, ASIC design and verification

  2015 — 2015

Skills

• Application-Specific Integrated Circuits (Asic)
• Asic Design
• Fpga
• Asic
• System Verilog
• Systemverilog
• Uvm
• Field-Programmable Gate Arrays (Fpga)
• C++
• Soc
• Cmos
• Universal Verification Methodology (Uvm)
• Perl
• Vlsi
• Digital Electronics
• Verilog
• Very-Large-Scale Integration (Vlsi)
• Linux
• Modelsim
• Asic Verification