Seshanna Katam
ASIC Physical Design Engineer
- Role
- Senior Asic Physical Design Engineer at Micron Technology
- Location
- Kurnool, AP, IN
- LinkedIn followers
- 500 followers
About Seshanna Katam
To secure a challenging position in VLSI Physical Design where I can effectively contribute my skills as a professional.7+ Years of Experience in VLSI Physical Design. Currently working at Micron Technology, Hyderabad.MS(Electronics & Communication) by Research from National Institute of Technology(NIT), Tiruchirapalli in 2016.Knowledge in-Experience on latest chip design process technology nodes like 16nm, 12nm, 6nm, 5nm-Experience in VLSI backend flow and methodology setup based on the PDK-Block level STA & Sign-off timing closure-Hands-on physical design experience from RTL to GDSII which includes Synthesis, Floor planning, power planning, Bump planning, place and route, CTS, STA, PV using industry standard tools-Hands on experience on full chip bump planning, RDL routing, block partioning and pin placement-DRC & LVS Cleaning-IR/EM Analysis and fixing EDA Tools:Synopsys -> ICC, ICCII, DC Compiler, Star-RCXT & PrimeTimeCadence -> Encounter, Innovus, Tempus, QRC
Experience
Senior Asic Physical Design Engineer
Jul 2019 — Present · Hyderabad, IN
Education
Jawaharlal Nehru Technological University
Bachelor of Technology (BTech)
2006 — 2010
National Institute of Technology, Tiruchirappalli
MS by Research
2013 — 2016
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