Seshank Varma

About Seshank Varma

With over 5 years of experience in silicon design and hardware engineering, I currently work as a Senior Silicon Design Engineer at Google. My role focuses on ASIC and RTL development, where I leverage deep expertise in Verilog and VHDL to contribute to efficient hardware design and verification processes. Collaborating with cross-functional teams, I aim to deliver high-quality and innovative silicon solutions. My prior experience as an ASIC RTL Design Engineer at Google and Senior Lead Engineer at Qualcomm allowed me to refine my skills in chip design, debugging, and hardware development. I am committed to supporting the creation of impactful, scalable, and high-performance hardware solutions that align with organizational objectives.

Experience

1. Sr Silicon Design Engineer

   Google

   Apr 2025 — Present · IN

Education

• Manipal Institute of Technology

  Master of Technology (MTech), Microelectronics

  2013 — 2015

• Narayana Junior College

  Intermediate, MPC

  2007 — 2009

• NSKK High School

  High School

  1995 — 2007

• DRK College Of Engineering and Technology (JNTU Hyderabad)

  Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering

  2009 — 2013

Skills

• Cadence Encounter
• Spyglass
• Rtl Design
• Verilog
• Cadence Virtuoso
• Soc
• Field-Programmable Gate Arrays (Fpga)
• C
• Cdc
• Debugging
• Very-Large-Scale Integration (Vlsi)
• System Verilog
• System on a Chip (Soc)
• Vlsi
• Cadence Virtuoso Layout Editor
• Linux
• Modelsim
• Analog
• Vhdl
• Simulations
• Cadence Spectre
• Perl
• Systemverilog
• Xilinx Ise
• Fpga
• Asic