Selvaganesh S

About Selvaganesh S

Experience 9+ years inHigh Speed Commerical,MotherBoards & Server Boards- 12 to 16 layers.ATE,Load boards & Probe card boards - 56 - 72 layers.Intel -x86 architecture - MLO, MLCx,LTCC HTC -Materials Selection -Stack Seperation include HDI,B&B vias - Lamination Consideration-TDR Calculation, Skew, Fibreweve adjustment.High Speed, HDI, Multi Chip Module, RF,SoC & Interposer - Intel FPGA, 112G & 56G Serdes PHY, Micro vias -3+N+3 Blind & Buried technologyTools - Expert in Cadence Allegro 16.6 - 17.4 & Altium designer 10 -22,Mentor Graphics- Expedition,Schematic - capture CIS, Altium Design, Expedition.Signal Integrity- Hyper Lynx, Cadence Sigrity & Ansys SIwavePower Integrity - Hyper Lynx & Ansys HFSS BOM Generation- Variants, Altium Vault,Cadence Version Control to Local SAP Connect. Multiples Variant Seperation in Single Schematic Structure IPC - PCB Standards following under Stack develop, Component Creation, Routing, deliverables, Fab & Assembly based on IPC PCB standardsAutomotive Standardization - Functional safety,EMC robustness,Thermal management,Reliability in harsh environmentsDFMA- CAM350 & VALOR.

Experience

1. Senior Design Engineer

   Pricol Limited

   Nov 2021 — Present · Coimbatore, IN

   Lead end-to-end PCB design for automotive instrument cluster products, from schematic capture to Gerber release. Collaborated closely with hardware, mechanical, and DFT teams to deliver high-speed, EMI-compliant multi-layer PCB designs aligned with automotive quality standards.Self Learn Contribution: 1.Independently Developed PCB internal documentation and design frameworks in compliance with BMW GS 95•••21, integrating IPC-6012 Class 3, and IEC 60664-1 parameters to optimize and competitive with High End PCB design for automotive safety, reliability, and cost-effectiveness.2. Solely Developed PCB internal documentation for Power Truck and High-Voltage EV PCB layout guidelines, including material selection strategies. Addressed the limitations of standard FR-4 (CTI Group which typically withstands <175V under Pollution Degree 2, by applying galvanic isolation techniques and validating creepage/clearance using & conformal coating. Able to withstand of 300–350V operation on cost-effective FR-4, which will be implemented in future BMS and EV projects.

Education

• S N R Sons College

  Bachelor of Science - BS, Electronics and communication Engineering

  2013 — 2016

• Bharathiar University

  Master of Science - MS, Computer Engineering