Kapil Sehgal
Principal Engineer @Intel
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WORK HISTORY
Principal Engineer @Intel
Lead SOC Floorplan architect for entire dGFX product stackDrive floorplan pathfinding activity with product and architecture teams to improve Perf/$, guide product features, process selection, and optimize product cost. Work with package and platform teams to find floorplan solutions leading to best overall thermals, power delivery, noise, and latency. Drive options to improve package size and reduce layer countConcurrently plan multiple product SKUs to maximize chip to chip reuse Drive area optimization across the business unit with key stakeholders. Identify key flow initiatives, optimal construction techniques, provide feedback on floorplan improvements across all projects and define best known practices across the team.
EDUCATION
University of Toronto
Bachelor of Applied Science (B.A.Sc.), Computer Engineering
ABOUT KAPIL SEHGAL
Highly experienced Physical Design leader with extensive Floorplan Architecture experience in complex SOC and GPU products. Hands-on experience with tech nodes down to TSMC-N3, and across multiple foundries. Experience with monolithic and Multi-chip designs.Experience with power-gated / DFT designs at both the chip and tile levels.SOC and block level experience with CTS, Place and Route, and Timing closure. 20 years of Physical Design experience, and over 14 years of experience as technical team leader owning and delivering SOC/GFX products on schedule and within budget.
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