Seema Dhull
Semiconductor Circuit Designer @ GlobalFoundries | MRAM Memory Architecture | Central R&D
- Role
- Principal Engineer at GlobalFoundries
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Seema Dhull
Innovative and detail-oriented Circuit Designer with 7 years of total experience (2 years industrial experience at GlobalFoundries and 5 years academia experience at IIT Roorkee) specializing in the design and development of MRAM (Magnetoresistive Random Access Memory) circuits. Expertise in developing high-performance, low-power memory systems and a deep understanding of MRAM architecture, including STT-MRAM (Spin-Transfer Torque MRAM), toggle MRAM, SOT-MRAM (Spin-Orbit Torque MRAM) and magnetic DW MRAM ( Domain Wall MRAM). Proficient in designing read/write circuits, sense amplifiers, and peripheral circuits essential for memory functionality, with a focus on optimizing speed, power consumption, and reliability. • Skilled in using industry-leading design tools such as Cadence and Synopsys for simulation, modeling, and verification of memory circuits. Demonstrated success in taking designs from concept through tape-out, including reliability analysis, circuit checks, critical path circuit designing, and meeting stringent performance criteria. Adept at addressing challenges unique to MRAM technology, including process variations, thermal effects, and non-volatility requirements. • A strong team player with excellent communication skills, capable of collaborating with cross-functional teams to drive MRAM-related projects from concept to production. Committed to advancing memory technology with a continuous focus on innovation, quality, and efficiency. • Had successful international research collaborations with Nanyang Technological University, Singapore, Delft University of Technology, Netherlands, and Virgina Commonwealth University, U.S.A. • Committed to hard work and in-depth analysis, have authored 26 articles (9 as a first author) in top Journals such as (TNNLS, TED, TMAG, TNANO), AIP APL, IOP SST, and international conferences such as DAC, NMDC, NANO.
Experience
Principal Engineer
May 2023 — Present · Bengaluru, IN
Circuit designer, MRAM memory architecture
Education
Deenbandhu Chhotu Ram University of Science & Technology, Murthal(Sonepat)
Post Graduation,Master of Technology (M.Tech.), ECE(VLSI DESIGN)
2015 — 2017
Indian Institute of Technology, Roorkee
Doctor of Philosophy - PhD, Spintronics Devices/Circuits
Sunshine Public School,Kaithal
Senior School, PCM
2008 — 2010
UIET KURUKSHETRA
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
2011 — 2015
K.V.M SEN. SEC. SCHOOL, PAI (KAITHAL)
HIGH SCHOOL
2008
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