Sedat Sayar
Hw Design Staff Verification Engineer @STMicroelectronics
Grenoble, FR
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Nov 2017 — Present
Hw Design Staff Verification Engineer @STMicroelectronics
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Grenoble, FR
EDUCATION
1991 — 1993
UFR Sciences et Techniques de Besancon
M.S.T Automatisme et Electronique Industrielle, Option Optronique
1989 — 1991
Université Joseph Fourier de St Martin d'Hères
D.U.T Génie Electrique et Informatique Industrielle, Option Micro-Onde
1987 — 1989
LTE de Voiron
Baccalauréat E - Math Sup T
SKILLS
AtbNcsimBeekeepingSystem VerilogPatent SearchingVhdlTcl-TkVerilogAssembly LanguagePatent ApplicationsSketchupXilinxCadstarProgram CacheSocNexusAsicIccJtagDebuggingArmApbTest Case GenerationAhbOrcad Capture CisFunctional VerificationData CacheSpecman
ABOUT SEDAT SAYAR
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