Shashi Bhushan Chauhan

About Shashi Bhushan Chauhan

Field Applications Engineer at Future Electronics, passionate about digital circuit design and FPGA implementation. Skilled in translating customer requirements into innovative FPGA solutions using Microchip FPGAs and evaluation boards. Beyond work, I’ve built personal projects like a digital watch and an FPGA-based LED matrix display, reflecting my interest in hands-on design, RTL coding, and debugging.Experience at Future Electronics (FPGA Focus)- RTL Design: Interfaced and validated uPROM to LSRAM IP controller- Memory Systems: Validated DDR3L/DDR3/DDR4 IP controllers on FPGA/SoC- Hardware Debugging: Used Identify Debug & oscilloscopes for real-time validation- Peripheral Interfaces: Validated UART, SPI, I2C IPs with RTL control blocks- DSP & Algorithms: Generated sine & cosine using DDS & CORDIC IP in Libero SoC- Communication Systems: Designed RTL for UART loopback data testing- AI/ML Applications: Implemented face detection using VectorBlox AI/ML on FPGA with MIPI camera input- LED Display Matrix: Developed smooth-scrolling text display on 8×8 LED matrix modules using SPI communication on PolarFire SoC FPGA.Key Skills- FPGA Platforms: Microchip (PolarFire, SmartFusion), Xilinx- Digital Design: RTL (Verilog, SystemVerilog), UVM- Architectures: RISC-V, Embedded Systems (C)- EDA Tools: Libero SoC, QuestaSim, Quartus Prime- Circuit & PCB: Design fundamentals, repair, debugging- Extra Edge: Strategic thinker & problem solver, sharpened through competitive chess Let’s Connect! – I’m always open to discussing FPGA innovations, embedded systems, and digital design.

Experience

1. Field Application Engineer

   Future Electronics

   Oct 2023 — Present · Bengaluru, IN

   RTL Design: Interfacing and validating the uPROM to LSRAM IP controller.2). Validation of DDR3L/ DDR3/ DDR4 IP controller on FPGA and FPGA SoC.3). FPGA Board Hardware debugging by Identify Debug and validating the real time clock on oscilloscope.4). FPGA IP validation of UART, SPI, I2C Interface and with the help of RTL controlling block.5). Generation of Sine & Cosine by using the DDS & CORDIC IP in Libero SoC Design Suit.6). RTL Designing for Loopback data through UART Interface.7). Face Detection on Microchip FPGA Board by using Vector Blox AI/ML by capturing the video through the MIPI Interfaced camera Module and recognising the Age.

Education

• Bundelkhand University (BU), Jhansi

  Bachelor of Technology - BTech, Electronics and Communication Engineering

  2011 — 2015

• Bhabha University

  Master of Technology - M.Tech, VLSI Design

• Bihar School Examination Board (BSEB)

  High School

  2007 — 2008