Sayicharan N
Design verification engineer
- Role
- Design Verification Engineer at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sayicharan N
Having 3+ years of experience on GLS Verification of 6nm, 7nm and 10nm where the setup is…
Experience
Design Verification Engineer
Mar 2022 — Present · Bangalore, IN
Worked on Gate Level Simulation of SoC.2. Ownership on various partitions of sub-system on the particular die, which hadmore than 10 partitions.3. Worked on all flavors of GLS, i.e, Power Aware, Zero delay and Standard delay format.4. Debugged failing cases and concluded with resolving issues like X propagation,force mismatch etc.5. Reported setup-hold violations in SDF GLS.6. Debugged the complex issues in the netlist like X propagation from non-resettableflops, race around condition issues, mismatch in forcing of RTL and netlist etc.
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