Sayani Mahapatra
Logic Design Engineer at Microsoft/Ex Intel | VLSI | Floorplanning | Place and Route - PNR | TCL and PERL | Design Rule Checking | Clock Tree Synthesis | Static Timing Analysis | Verilog | Red Hawk
- Role
- Logic Design Engineer at Microsoft
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sayani Mahapatra
ASIC Physical Design Engineer with 4 years & 9 months of experience in technology nodes across multiple foundries including INTEL, TSMC in 10nm 7nm nodes. Primarily worked as a Physical Design Engineer with major focus in block level design implementation for chips(memory/IPU).• Hands on experience in various EDA Tools Synopsys ICC2 Fusion Compiler DC Compiler Cadence Innovus P&R.• Worked independently in RTL to GDS Implementation including P&R (Place and Route) STA (Static Timing Analysis). Also involved in timing, signoff and other aspect of Physical designProven ability of learning new concepts quickly and applying the skills to meet business goals on time.Strong Engineering background with a Masters in Technology(MTech) in VLSI Design from Institute of Technology, Nirma University
Experience
Logic Design Engineer
Sep 2023 — Present
Education
Nirma University
VLSI Design
2016 — 2018
Sir Padampat Singhania University
Bachelor's degree
2011 — 2015
Skills
- Supply Chain Management
- Manufacturing
- Autocad
- Leadership
- Customer Service
- Engineering
- Product Development
- C
- English
- Electrical Engineering
- Electronics
- Microsoft Word
- Team Leadership
- Teamwork
- Lean Manufacturing
- Microsoft Office
- Microsoft Excel
- Powerpoint
- Solidworks
- Matlab
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