Sayan Sarkar

About Sayan Sarkar

I am a passionate semiconductor engineer in LTD, Intel Corporation with a voracious aptitute for learning and engineering curosity. I have contributed heavily to the cleans process development and supporting product cycles of cpus and data centers maufactured using the most advanced process nodes of Intel 7/Intel20A/Intel18A especially in the novel backside power delivery (powervia) segmentI obtained my PhD at the University of Utah, under the supervision of Prof Michael Free and Prof Prashant Sarswat where my research was based on dopants induced optimization of selected Dirac materials based on first principle calculations. My research focused on improving the electronic and optical properties of 2D materials like phosphorene, 3D Dirac materials like tellurides for photovoltaic, memory and thermoelectric applications. Top Noteworthy Accomplishments/ Achievements1. I have published 18 impactful articles as a primary/co-author in prestigious peer-reviewed high-impact journals of American Chemical Society, Nature, Elsevier, American Physical Society and also served as a peer-reviewer of 30 manuscripts in international reputed journals of Royal Society of Chemistry, American Chemical Society, Elsevier and MDPI.2. I was duly elected as a full member of Sigma XI, The Scientific Research Honor Society.3. I was selected as a guest associate editor in two impactful European journals Frontiers in Energy Research and Frontiers in Electronic Materials, where I served in editorial role for leading two research topics on Dirac Materials and 2D materials for thermoelectric, spintronics and energy harvesting applications4. I contributed to best practices of subfin elimination in Intel’s innovative Backside Power delivery Process (BSPDN) and will be used in Intel’s most advanced 20A/18A manufacturing process node, the subsequent invention disclosure filing (IDF) on this innovation was deemed as outstanding by the semiconductor process committee and was filed for US patent (Case#AF1808-US).Interests- Material research (Dirac materials) for improvement of electronic, memory and thermoelectric properties, Semiconductors, Backside Power deliverySkills-Density functional theory-Materials Synthesis-Materials Characterization tools : SEM, EDS, XRD, RAMAN, FTIR, UV-VIS, Impedance Spectroscopy, Micro-fabrication: Tokyo Electron based Etch toolsNano-fabrication tools- SPC, Klarity, E3, MES, Automation systemsProgramming-Python, JMP, SQL, Quantum Expresso, crystal Maker (DFT)Softwares/Packages-Qunatum Expresso, Quantumwise, Virtual Nanolab, SciPy, NumPy

Experience

1. Staff Engineer, Module Development

   Intel

   May 2025 — Present · Portland, OR, US

Education

• Jadavpur University, Kolkata

  Bachelor’s Degree, Metallurgical and Material Engineering

  2011 — 2015

• University of Utah

  Doctor of Philosophy (Ph.D.) Advisors : Dr Michael Free and Dr Prashant Sarswat

  2015 — 2019