Sayan Sarkar

About Sayan Sarkar

I am a passionate semiconductor engineer in LTD, Intel Corporation with a voracious aptitute for learning and engineering curosity. I have contributed heavily to the cleans process development and supporting product cycles of cpus and data centers maufactured using the most advanced process nodes of Intel 7/Intel20A/Intel18A especially in the novel backside power delivery (powervia) segment I obtained my PhD at the University of Utah, under the supervision of Prof Michael Free and Prof Prashant Sarswat where my research was based on dopants induced optimization of selected Dirac materials based on first principle calculations. My research focused on improving the electronic and optical properties of 2D materials like phosphorene, 3D Dirac materials like tellurides for photovoltaic, memory and thermoelectric applications. Top Noteworthy Accomplishments/ Achievements 1. I have published 18 impactful articles as a primary/co-author in prestigious peer-reviewed high-impact journals of American Chemical Society, Nature, Elsevier, American Physical Society and also served as a peer-reviewer of 30 manuscripts in international reputed journals of Royal Society of Chemistry, American Chemical Society, Elsevier and MDPI. I was duly elected as a full member of Sigma XI, The Scientific Research Honor Society. I was selected as a guest associate editor in two impactful European journals Frontiers in Energy Research and Frontiers in Electronic Materials, where I served in editorial role for leading two research topics on Dirac Materials and 2D materials for thermoelectric, spintronics and energy harvesting applications 4. I contributed to best practices of subfin elimination in Intel’s innovative Backside Power delivery Process and will be used in Intel’s most advanced 20A/18A manufacturing process node, the subsequent invention disclosure filing (IDF) on this innovation was deemed as outstanding by the semiconductor process committee and was filed for US patent (Case#AF1808-US). Interests - Material research (Dirac materials) for improvement of electronic, memory and thermoelectric properties, Semiconductors, Backside Power delivery Skills -Density functional theory -Materials Synthesis -Materials Characterization tools : SEM, EDS, XRD, RAMAN, FTIR, UV-VIS, Impedance Spectroscopy, Micro-fabrication: Tokyo Electron based Etch tools Nano-fabrication tools- SPC, Klarity, E3, MES, Automation systems Programming -Python, JMP, SQL, Quantum Expresso, crystal Maker (DFT) Softwares/Packages -Qunatum Expresso, Quantumwise, Virtual Nanolab, SciPy, NumPy

Experience

1. Module and Yield Integration Engineer

   Intel

   May 2019 — Present · Portland, OR, US

   Qualification and conversion of state-of-the-art Tokyo Electron Wet Etch tools by extensive tool qual white papers to ensure quality and reliability standards of latest process nodes• Support various focus teams for wet platforms deliverables in novel backside power delivery (Tyche process) in Intel 20A/18A• Sustenance of Wet etch tools by regular preventive maintenance, monitoring control charts in SPC, matching the tool parameters to the rest of the fleet using PCSA and real time parameter monitoring in E3 systems (Applied Materials)• Development of auto-monitor and automation systems in MES to track tool health and optimized performance• Process optimization/defect reduction by analyzing failure modes in Klarity, DART (Defect Automated Real Time Monitoring system), Crystal Ball• Understanding and development of FMEA to determine severity, occurrence, detection of various failure modes for risk assessment and mitigation of risk by lowering RPN• Analysis of large data sets for tool parameters using JMP/SQL; support auto-generated queries through SQL for convenient tracking of MES, tool, die metrics in high volume manufacturing• Supporting process development and cost reduction through recipe development, DOE in JMP, and documentation in white paper • Supporting high volume manufacturing, technology roadmap and product development cycles in 1272/1274/1274• Received LTD Divisional Award and Deparemental Divisional Awards for defect reduction, RISO improvement and cost savings in cleans segement of Intel 7 nm process• Contributed to best practices of subfin elimination in Intel’s innovative Backside Power delivery Process and will be used in Intel’s most advanced 20A/18A manufacturing process node, the subsequent invention disclosure filing (IDF) on this innovation was deemed as outstanding by the semiconductor process committee and was filed for US patent (Case#AF1808-US).

Education

• Jadavpur University, Kolkata

  Bachelor’s Degree, Metallurgical and Material Engineering, First Class Honors (8.30 out of 10)

  2011 — 2015

• University of Utah

  Doctor of Philosophy (Ph.D.) Advisors : Dr Michael Free and Dr Prashant Sarswat, 3.95 out of 4.0

  2015 — 2019