Sayan Adhikary
SRAM Design Engineer @NVIDIA || Ex-Senior Analog Design Engineer at Synopsys
- Role
- Senior Asic Design Engineer at NVIDIA
- Location
- Asansol, WB, IN
- LinkedIn followers
- 500 followers
About Sayan Adhikary
Having 3+ years experience as a Senior Analog Design Engineer in Synopsys. Responsible for designing differentiated IOs like Fail-safe/ Fail-tolerant/ Non Fail safe/ High Voltage Management IOs on 3nm, 7nm TSMC technology node. Worked on I3C/ GPIO bus protocol. Demonstrated strong innovation skill by solving complex design issues and filed multiple patents on it (1 granted, 3 more in pipeline)Worked on reference signal generation circuitry, bandgap design, two stage miller compensated op amp design, folded cascode based OTA design. Having strong understanding of small signal analysis, amplifier design, current mirrors, biasing techniques, compensation schemes, control systems, high voltage level shifter, Predriver, Driver design, Schmitt Trigger design. Good understanding of ESD, Simultaneous switching noise.Having sound knowledge in SRAM self timing, bitcell analysis, Sense amplifier design, Wordline driver (pre decoding/post decoding), Write driver, column mux, hierarchical array design with strong grasp on STA and BIST.
Experience
Senior Asic Design Engineer
Aug 2025 — Present · Bangalore, IN
SRAM Memory Compiler Design
Education
ASANSOL RAMAKRISHNA MISSION HIGH SCHOOL
Class 10th
2009 — 2013
ASANSOL OLD STATION HIGH SCHOOL(H.S)
class 12, SCIENCE
2013 — 2015
Indraprastha Institute of Information Technology, Delhi
M.TECH , VLSI AND EMBEDDED SYSTEMS
2020 — 2022
INSTITUTE OF ENGINEERING AND MANAGEMENT
B.TECH, ECE
2015 — 2019
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