Sayam Raja

About Sayam Raja

To pursue a challenging career in a leading front end VLSI Company which will allow me to use mytechnical skills to increase the worth of the company and to contribute to the development of new technology in the future.• Handling IPU deployment in SOC with Ryzen processor.• 4 Years 3 months working Experience in Synopsys USB SG team • Worked in Synopsys USB SG team.• Worked on USB (Version 2.0/3.0/3.1/3.2) link layer VIP issues.• Worked on verification of Synopsys 2.0,3.0,3.1,3.2 USB controller. • 3 years 8 months of working experience in PerfectVIPs as ASIC Verification Engineer.• Worked to verify PCIe GEN4 IP in EdgeQ SOC by writing different scenario.• Worked to verify PCIe GEN4 Redriver Regera of ON semiconductor using mentor QVIP. Worked to create full UVM ENV, integrated QVIP,achieved 100% functional coverage of physical layer. Worked on immediate assertions.• Worked to verify PCIE1x2_ADL_UH Intel Model. Worked on RTD3(PMETO),AUTO_PG,CLKREQMSG,CLKGATING,VNN,CPG,L0s, Equalization features. Got RTL/BFM/PHY/MOAT Issue. Improved coverage.• Worked to verify PCIE_ADL_S Intel Model. Worked on AUTO_PG,CLKREQMSG,CLKGATING,VNN,CPG,L0s, Equalization features. Got RTL/BFM/PHY/MOAT Issue. Improved coverage.• Worked on PCIe GEN4 Verification Project involved in debugging the LTSSM related issue of Synopsys VIP.• Worked on Verification of SPI,AXI4,APB interface based design, developed RAL environment.• Worked on Verification of single clock synchronous RAM,FIFO.

Experience

1. Mts Silicon Design Engineer

   AMD

   Mar 2025 — Present · Bangalore Urban, IN

Education

• St Xavir Collage Ranchi

  Intermediate , Scince

  2011 — 2013

• Silicon Institute of Technology (SIT), Bhubaneswar

  Bachelor of Technology, Electrical and Electronics Engineering

  2013 — 2017

• Birla Institute of Technology and Science, Pilani

  Master of Technology - MTech, Microelectronics

  2021 — 2023