Savitanandan Patidar
Design Engineer
- Role
- Design Engineer at HCLTech
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Savitanandan Patidar
I have a great interest in VLSI circuit and layout design. Experienced in Planner MOSFET & FinFET based design and process. Hands on experience in EDA tool like Cadence Virtuoso and Synopsys Custom Compiler for Schematic and Layout Editing. Layout experience of Analog, Memory and Standard Cells block and subblocks. Good understanding of Parasitic Extraction Flow and Developnent using StarRC, Calibre and Quantus. Research Experienced in design MOSFET simulation Model at cryogenic temperature for space application.
Experience
Design Engineer
Oct 2024 — Present · Bengaluru, IN
Education
Vishwakarma Government Engineering College
Master's degree, VLSI Technology
Rajiv Gandhi Prodyogiki Vishwavidyalaya
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
Skills
- Analog Circuit Design
- C++
- Research
- Semiconductor Device
- Vhdl
- Microsoft Office
- Plc Programming
- Device Modeling
- C
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