Saurav Ranjan
Analog Design Engineer!! EX-ANALOG VLSI DESIGN INTERN @ FORZA SILICON AMETEK !! M.TECH ECE @ NIT - Warangal
- Role
- Analog Design Engineer at Alphacore Inc.
- Location
- Patna, BR, IN
- LinkedIn followers
- 500 followers
About Saurav Ranjan
As a dedicated graduate from NIT Warangal with a Master’s degree and a strong focus on Analog VLSI, I am deeply passionate about innovation and continually strive to stay at the forefront of industry advancements. Currently working in the field, I take pride in optimizing analog circuit performance and crafting efficient layout designs.My experience spans a wide range of analog blocks and methodologies, including:Analog IP Design: LDOs, Voltage Monitors, Comparator and High-Speed Level Shifters (HL & LH).Design Methodology: Proficient in gm/ID-based design, ensuring robust performance optimization across PVT corners and Monte Carlo simulations.Simulation & Verification: Skilled in pre- and post-layout simulations, with comprehensive validation through DRC/LVS checks and statistical analysis.Key Projects:Telescopic OTA – Designed and optimized for performance across process variations.Reference VDAC for LVDS VCM – Developed and validated across PVT and Monte Carlo corners for high reliability.Technology Proficiency: Hands-on experience with STMI IMG140 platforms, including 90nm, and 22FDX (GlobalFoundries) process technologies.With a strong foundation in analog design and a commitment to excellence, I am eager to contribute to pioneering innovations in analog VLSI research and development.
Experience
Analog Design Engineer
Jun 2025 — Present
Designed a high Power Supply Rejection Ratio (PSRR) LDO under worst-case conditions, achieving a high PSRR with amaximum voltage drop of 80 mV with 0.85 V LDO output voltage which is used in DAC. Verified circuit performance across Process, Voltage, and Temperature (PVT) variations to ensure robustness and reliability.– Verified a 12-bit, 10 GSPS DAC by performing RC extraction, LVS verification, and comprehensive pre-/post-layoutsimulations at the top level; achieved 65 dB SFDR compliance.– Technology - 22FDX technology of Global Foundry– Tools used- Cadence Virtuoso, ADE assembler, Maestro,spectre
Education
National Institute of Technology Warangal
M.Tech
2022 — 2024
Future Institute Of Engineering and Management
Bachelor of Technology - BTech
2015 — 2019
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