Saurav Nigam

About Saurav Nigam

Semiconductor engineering leader with more than 17 years of experience advancing lithography, patterning integration, and manufacturing ramp across leading-edge technology nodes. My work has focused on translating lithography capability, equipment innovation, and integrated process development into manufacturable solutions that enable high-volume semiconductor production.At Intel, I have led teams spanning lithography, overlay, metrology, and process integration while managing EUV scanner fleets supporting advanced-node development and manufacturing ramp. My work includes delivering large-scale manufacturing improvements such as a 42% scanner productivity enhancement across ASML platforms and equipment reliability innovations that generated approximately $59M in cost savings.I have been closely involved in multiple technology nodes including 18A, 7nm, 10nm, and 14nm, contributing across lithography capability, integrated patterning development, device architecture improvements, and technology transfer to high-volume manufacturing.My work often sits at the intersection of equipment capability and process integration. I have collaborated extensively with ASML engineering teams on scanner capability improvements, EUV platform qualification, and next-generation lithography readiness.Areas of focus include:• EUV lithography and advanced patterning• Overlay strategy and lithography process control• Integrated process and device architecture development• Advanced-node manufacturing ramp and TD → HVM technology transfer• Equipment capability and productivity optimizationI am passionate about building strong engineering teams, mentoring future technical leaders, and creating collaborative environments where innovation and disciplined execution can thrive.

Experience

1. Engineering Manager Senior Principal Engineer

   Intel

   Jan 2019 — Present · Hillsboro, OR, US

   Lead lithography and patterning technology development supporting advanced semiconductor nodes, including 18A technology development and manufacturing ramp. Provide strategic leadership across scanner capability, overlay control, and integrated patterning development while coordinating large cross-functional engineering teams within a matrixed organization.Technology Strategy & Roadmap Leadership • Co-define lithography and overlay capability roadmaps with senior lithography leadership, integrating requirements from device, process integration, and manufacturing organizations. • Align technology capability plans across internal engineering groups and external equipment partners to support advanced node development.Ecosystem & Vendor Collaboration • Work directly with ASML and KLA engineering organizations to align equipment capability with future lithography and overlay requirements. • Influence scanner productivity, overlay accuracy, and patterning capability development across EUV and immersion platforms.Organizational Leadership & Program Design • Define focus-team structure and engineering program organization across lithography and overlay development initiatives. • Select and allocate engineering talent across scanner and overlay to support critical development programs. • Provide technical leadership across large cross-functional engineering teams coordinating 100+ engineers within a matrixed development organization.Advanced Node Technology Development • Led lithography and integration initiatives supporting Intel 18A technology, including qualification and insertion of ASML NXE:3800 EUV platforms.Technology Transfer & Manufacturing Ramp • Serve as technology transfer lead bridging Technology Development and High-Volume Manufacturing organizations. • Work closely with manufacturing teams to stabilize process capability and accelerate yield ramp for advanced nodes.

Education

• Carnegie Mellon University

  Doctor of Philosophy - PhD, Materials Science and Engineering

• Carnegie Mellon University

  PhD, Materials Science

  2003 — 2008

• University of Florida

  MS, Chemical Engineering

  2001 — 2002

• Indian Institute of Technology, Roorkee

  BTech, Chemical Engineering

  1997 — 2001

Skills

• Product Development
• Semiconductors
• Process Engineering
• Afm
• Research and Development (R&D)
• Process Simulation
• Intel
• Thin Films
• Project Management
• Design of Experiments
• Manufacturing
• Characterization
• Photolithography
• Materials Science
• Failure Analysis
• Management
• R&D