Saurav More

About Saurav More

Physical Design Engineer with 4+ years of experience in ASIC implementation and physical verification. Strong hands-on expertise in end-to-end PD flow including floorplanning, power planning, placement, CTS, routing, timing closure, DFM, and physical verification. Experienced in HV OpenRail flow and collaborating closely with HV owners. Currently contributing as a PV lead, coordinating and managing cross-functional teams to drive clean signoff. Proficient in ICC2, Fusion Compiler, Cadence Innovus, and Linux. Passionate about delivering high-quality designs and continuously learning in the semiconductor domain.

Experience

1. Physical Design Engineer

   Intel

   May 2023 — Present · Bengaluru, IN

   Physical Design & verification,Signoff & IntegrationFloor-planning, Place and Route, CTS, Physical Verification (DRC/LVS), PDN, Timing Closure & RV(EM & IR).> Currently working on Intel3, Intel20A, Intel18A technology, handling multiple partitions with quality.> Expertise in TSMC 3nm technology, signoff, cleanup, Partition convergence, Reliability Verification and tapein.>Working with the ADE (Automatic Design Execution)tool to automate design workflows.>Expertise in review and convergence of Media, IPU, subsystems and SOC.>Expertise in Fusion Compiler, ICC2, Cadence Innovus, Flowtracer, ICWB.> Knowledge of Floorplan, Placement, Routing and DFM.> Experience in automation of process, ADE & Falcon.> Good understanding of TCL & perl.

Education

• Vidyadham junior college of science Shirur

  HSC, PCMB

  2015 — 2017

• Savitribai Phule Pune University

  Master of Science - MS, Electronic Science (VLSI Design)

• Fergusson College

  Bachelor of Science - BS, Electronic Science

  2017 — 2020