Saurav Jhalani
Design Engineer at Apple
- Role
- Design Engineer at Apple
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Saurav Jhalani
Complete Place and Route Flow experience i.e. RTL to GDSII on 28nm and Fin-Fet…
Experience
Design Engineer
Aug 2020 — Present · San Diego, CA, US
Skills
- Verilog
- Application-Specific Integrated Circuits (Asic)
- Programming
- Synopsys Tools
- Vhdl
- C++
- Asic
- Mixed Signal
- Perl
- Cadence Virtuoso
- Modelsim
- Physical Design
- Synopsys Primetime
- Integrated Circuit Design
- Microprocessors
- Xilinx
- Systemverilog
- Tcl
- Calibre
- Vlsi
- Signal Integrity
- Rtl Design
- Soc
- Very-Large-Scale Integration (Vlsi)
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