Saurabh Vats
Principal Design Engineer at Marvell Technology
- Role
- Principal Design Engineer at Marvell Technology
- Location
- Palo Alto, CA, US
- LinkedIn followers
- 500 followers
About Saurabh Vats
Experienced Analog/Mixed Signal (AMS) IC/Circuit Design EngineerWorked successfully on numerous products, from conception to launch, with large and small teams, in diverse roles. Adept with deep sub-micron CMOS (40nm,28nm,16nm(FinFET)) and BiCMOS processes. Extensive PCB design/layout background.B.Tech from IIT Delhi, MSEE from Stanford. 2 Patents, 1 paper in ISSCC.Keywords: Analog, Mixed-Signal, RF, IC Design, PCB design, Cadence Design Suite, CMOS, BiCMOS,16nm
Experience
Principal Design Engineer
Feb 2026 — Present · San Francisco, CA, US
Education
Stanford University
MS, Electrical Engineering
2006 — 2007
Indian Institute of Technology, Delhi
B. Tech, Electrical Engineering
1996 — 2000
Skills
- Integrated Circuit Design
- Adcs
- Soc
- Analog
- Labview
- Cadence
- Ic
- Wireless
- Low-Power Design
- Vlsi
- Semiconductors
- Cmos
- Integrated Circuits (Ic)
- Rf
- Mixed Signal
- Circuit Design
- Sensors
- Bicmos
- Asic
- Pll
- Analog Circuit Design
- Cadence Virtuoso
- Debugging
- Silicon
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