Saurabh Tomar
Senior Silicon Design Engineer | Physical Design l Full chip clocking | Ex- Intern@ Intel | BITS Pilani, Pilani
- Role
- Senior Silicon Design Engineer at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Saurabh Tomar
An Aspiring Engineer with the aim of learning and exploring various fields of VLSI domain enthusiastically.Had a good exposure to VLSI Physical Design during Internship and eager to dig it even more.
Experience
Senior Silicon Design Engineer
Dec 2023 — Present · Bengaluru, IN
Education
Birla Institute of Technology and Science, Pilani
Master's degree, Microelectronics
2018 — 2020
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