Saurabh Singh
SOC/IP Lead Design Verification Engineer @Texas Instruments | Ex Intel | BITS Pilani
- Role
- Lead Design Verification Engineer at Texas Instruments
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Saurabh Singh
Interested in IP/SOC Verification.Currently working on PCIE Gen3/4/5/6/7 and CXL Gen 1/2/3 protocol (Logical Physical layer) IP Validation in Intel Server XEON platform. Have also worked on PCIE IIO Subsystem verification, DFD verification and CSR (Register) Design & Verification• Languages: System Verilog, Verilog, VHDL, C, C++, Perl, system RDL• Validation methodologies : OVM,UVM/Saola, Assertion, Coverage
Experience
Lead Design Verification Engineer
Nov 2025 — Present · Bengaluru, IN
Education
AJAY KUMAR GARG ENGINEERING COLLEGE, GHAZIABAD
Bachelor of Technology (BTech), Electronics and communication engineering
2008 — 2012
Birla Institute of Technology and Science, Pilani
Master of Engineering (M.Eng.), Microelectronics
2012 — 2014
Skills
- Perl
- Asic
- Vhdl
- Turbo C++
- Verilog
- Microelectronics
- Cadence Skill
- Matlab
- Digital Circuit Design
- System Verilog
- Rtl Verification
- System Rdl
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.