Saurabh Saxena

Experience

1. Director of Engineering

   Intel

   Jul 2025 — Present · Bengaluru, IN

Education

• Motivational Pathway

  B.Tech, Electronics & Communication

  2000 — 2004

• Pune University

  P G Diploma, VLSI

Skills

• Soc
• Systemverilog
• Rtl Design
• Arm
• Uvm
• Static Timing Analysis
• Functional Verification
• Modelsim
• Specman
• Vhdl
• Debugging
• Ncsim
• Timing Closure
• Rtl Coding
• Vlsi
• Eda
• Amba Ahb
• Fpga
• Asic
• Integrated Circuit Design
• Physical Design
• Verilog
• Tcl
• Vmm
• Open Verification Methodology
• Formal Verification