Saurabh Goel

About Saurabh Goel

Design Verification Engineer at Microsoft with 13+ years of industry experience in building scalable verification environments from scratch using SystemVerilog and UVM. Currently leading verification for the vector processing unit of Maia—Microsoft’s custom AI accelerator chip. I architect and implement verification strategies for custom ISA execution using Assembly, SystemVerilog, UVM, and Siemens SLEC C2RTL. Skilled in computer architecture, microarchitecture, JTAG, AXI, and Python scripting. Familiar with post-silicon bring-up, test vector generation, ATPG, and gate-level simulations.

Experience

1. Principal Verification Engineer

   Microsoft

   Sep 2024 — Present · Redmond, WA, US

   Principal Design Verification Engineer at Microsoft, leading verification for the vector processing unit of Maia—Microsoft’s custom-designed AI accelerator chip. I architect and implement verification strategies for custom ISA execution using Assembly, SystemVerilog, UVM, and Siemens formal SLEC C2RTL. My work ensures functional correctness, performance alignment, and robust coverage across high-performance compute architectures.

Education

• University of Colorado Boulder

  Master's degree, Embedded Systems; Electrical and Computer Engineering

  2010 — 2012

• Visvesvaraya National Institute of Technology

  B.Tech, Electronics and Communication Engineering

  2006 — 2010

Skills

• Computer Architecture
• Cache Coherency
• C
• Compiler Design
• Uvm
• Systemverilog
• Compiler Construction
• Soc
• Specman
• Python
• Functional Verification
• Multithreading
• L2/L3 Protocols
• Verilog
• Debugging
• Fpga
• X86 Assembly
• Asic
• Mips
• Firmware
• Android Development
• Perl
• Raid
• Java
• C++