Saurabh Ravindra Deshmukh

About Saurabh Ravindra Deshmukh

I’m a Machine Learning Engineer focused on bringing advanced Deep Learning models to life on FPGA‑based edge AI systems. I work across the full stack—training and optimizing CNNs (YOLOv11, YOLOv8, SqueezeNet, ResNet, SSD, MobileNetV1/V2), applying aggressive 8‑bit and 2/4/8‑bit quantization, and deploying them efficiently on Lattice FPGAs.I designed hardware accelerators, resource‑aware compute modules, and flexible data‑stream engines built for next‑generation CNN architectures. I also developed the full neural compiler toolchain—network scheduling, memory management, layer merging, quantization, and optimization pipelines for ECP5, UltraPlus, and CrossLink‑NX devices.

Experience

1. Staff Engineer-machine Learning (Sw)

   Lattice Semiconductor

   Jun 2018 — Present · San Jose, CA, US

   Deep Learning- Trained Convolutional Neural Network models for edge applications on TensorFlow and PyTorch platforms and deployed them on FPGA devices- Explored, customized, and trained YOLOv11, YOLOv8, SqueezeNet, ResNet, SSD, MobileNetV1, and MobileNetV2 network architecture models with layers supported by the ML engine, using 8‑bit weights and 2/4/8‑bit activation quantization to reduce the overall model size.HW–SW Co‑Design- Architected HW accelerators for new CNN network architectures such as YOLOv8 and YOLOv11- Designed a compute module compatible with resource‑friendly quantization techniques and mapping- Designed a flexible data stream engine adaptable to model input dimensions, per‑layer channels, output dimensions, and hardware resources.Neural Compiler and Tool Development- Developed a neural network compiler, network scheduler, and memory management unit for Deep Learning models with 16‑bit and 8‑bit data sizes for ECP5, UltraPlus, and CrossLink‑NX FPGA devices from Lattice Semiconductor- Performed optimization, layer merging, partial‑layer execution, and quantization of Deep Learning models to speed up inference on FPGA devices without significant accuracy loss- Developed a tool for software simulation that emulates hardware engine execution in Python- Developed a reporting tool that provides layer‑wise estimation of memory usage and cycle counts for each device.

Education

• Vishwakarma Institute Of Technology

  Engineer’s Degree, Electrical, Electronics and Communications Engineering

  2010 — 2014

• Pemraj Sarada College,Ahemednagar

  High School

  2008 — 2010

• San José State University

  Master of Science (M.S.), Computer Engineering

  2016 — 2018

Skills

• Javascript
• C
• C++
• Ado.net
• Firmware
• Can Bus
• Jquery
• Html5
• Microsoft Office
• Microsoft Excel
• Java
• Matlab
• C#
• Sql
• Linux
• System Software
• Python
• Core Java
• Asp.net Web Api
• Html
• Asp.net Ajax