Saurabh Chaubey

Analog Design Manager @Texas Instruments

San Jose, CA, US
MOBILE NUMBERS
+16•••••••67

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WORK HISTORY

Apr 2024 — Present

Analog Design Manager @Texas Instruments

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Santa Clara County, CA, US

Managing a team of ~7 seasoned analog design engineers developing new custom PMIC products.

EDUCATION

2007 — 2012

Birla Institute of Technology and Science, Pilani

BE, Electrical & Electronics

2014 — 2016

University of Minnesota

Master’s Degree, Electrical and Electronics Engineering

2013 — 2018

University of Minnesota

Doctor of Philosophy (PhD), Electrical and Electronics Engineering

2007 — 2012

Birla Institute of Technology and Science, Pilani

Master's Degree, Physics

SKILLS

Mixed Signal DesignControl SystemAnalog Circuit DesignPower ConvertorsSignal ProcessingAlgorithmsLte Layer 2 Stack DevelopmentUnixSynopsys ToolsEclipseCCadence VirtuosoMixed SignalVerilogMatlabVlsi

ABOUT SAURABH CHAUBEY

I worked on the integrated power management as my PhD research area. I study and design integrated power conversion circuits for wide output current range and fast response DVS applications. My other research interests include PLL, oscillators and lower power analog design.

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