Saurabh Agrawal
Senior Silicon Design Verification Engineer | Google | Ex-Intel | IIT Delhi
- Role
- Senior Silicon Design Verification Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Senior Silicon Design Verification Engineer
Aug 2023 — Present · Bengaluru, IN
Education
Indian Institute of Technology, Delhi
Master’s Degree, VLSI Design
2015 — 2017
Government Polytechnic, Washim
Diploma, Electrical, Electronics and Communications Engineering
2007 — 2010
Maharashtra Institute of Technology
Bachelor’s Degree, Electronics and Telecommunication
2010 — 2013
Skills
- Xilinx
- Systemverilog
- Verilog
- Pcb Design
- Physical Design
- Multisim
- Asic
- Perl
- Embedded Systems
- Linux
- Sdsoc
- Very-Large-Scale Integration (Vlsi)
- C
- Python
- Vivado
- Static Timing Analysis
- Cadence Rtl Compiler
- Cadence Virtuoso Layout Editor
- System Verification
- Sta
- Cadence Encounter
- Embedded C
- Field-Programmable Gate Arrays (Fpga)
- Eagle Pcb
- Vivado Hls
- Rtl Verification
- Cadence Virtuoso
- Vhdl
- C++
- Microsoft Office
- Vlsi
- Matlab
- Windows 7
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