Saurabh Dwivedi
Senior Principal Design Engineer at Cadence | Ex TSMC| Ex Arm| Ex LSI(Broadcom)| Foundry Spice Model study | Foundry PDK Enablement | Foundry Technology DTCO Study (FINFET/GAA) | Foundry Interface | Physical Verification
- Role
- Senior Principal Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Saurabh Dwivedi
Over 16 years of experience in the VLSI industry, driving device modeling, foundry PDK enablement, and comprehensive validation across all components. Deep expertise in SPICE modeling, parasitic extraction, and process–circuit co-optimization, with a track record of partnering with leading foundries to deliver production-ready design ecosystems.• Spearheaded the development of advanced methodologies for early-stage PDK analysis, enabling insights for design and DTCO teams. Led the management and qualification of incoming foundry design kits and foundation IP, while establishing scalable IP QA frameworks leveraging industry tools such as Solido Crosscheck to ensure quality, reliability, and consistency at scale.• Recognized expert in BSIM-based device SPICE modeling, with deep proficiency across technology nodes spanning planar to advanced 3D architectures (FinFET, GAA). TOOL SKILLS :Synopsys Tools: Finesim, Hspice, StarRCXT, RAPID3d/Raphael, Quickcap, Hercules LVSCadence Tools: Pegasus LVS/DRC, Spectre, EMIR, Virtuoso, RelXpert, QRC, QRCFS(3d field solver) Fast Monte Carlo Mentor Tools: Calibre LVS, XRC, XACT3D, PERC, Solido HSMCAgilent Tools: ICCAPLab Tools: Wafer probe station handling.
Experience
Senior Principal Design Engineer
Aug 2025 — Present · Bengaluru, IN
Transfer & Continuation of Business from Arm to Cadence. Press
Education
Rajiv Gandhi Prodyogiki Vishwavidyalaya
B.E., electronics and communication
2004 — 2008
Indian Institute of Technology, Delhi
M. Tech., Applied Research in Electronics
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